CADENCE US
From company careers site
Design Engineer II
- Location
- NOIDA
- Work mode
- On-site
- Employment type
- Full-time
About the job
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Role Overview:
Key Responsibilities:
• • Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments. • Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis. • Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements. • Required Qualifications:
• B.Tech/M.Tech in ECE with
- B.Tech/M.Tech in ECE with
- Experience in SystemVerilog/UVM and C/C++ for architectural modeling.
- Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
- Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
- Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.
From CADENCE US's careers page (Workday), checked 29 Oct 2026.
How to apply
- Select Apply on cadence.com. It opens CADENCE US's own application form in a new tab, run on Workday.
- Fill in the form and upload your résumé there. Jobiwork never sees your application.
- CADENCE US will reply to you directly. No real employer asks you for money to apply.
Posted 1 Oct 2026 · checked 29 Oct 2026 · Report this job