Lead Software Engineer - Low Power Verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms.

As a Lead Software Engineer - Low Power Verification you will be responsible for improving the performance and usability of UPF debug features, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.

What you will do:

What we are looking for

• BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience. • Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL). • Strong debugging skills — root-cause analysis from logs, waveforms, traces, testcases, and user reports. • Ability to read, review, and reason about C++ code and object-oriented designs. • Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output. • Strong communication and technical writing skills — able to turn scattered debug evidence into clear, user-facing workflows. The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.