Senior Layout Design Engineer

Layout Design, Sr Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years translating analog circuit schematics into physical layouts that actually perform, not just pass DRC. You know that a GPIO layout is not just about routing metal, it is about understanding how a 2pF mismatch or a 10-micron shift can break ESD performance or skew I/O timing in ways the schematic never predicted. You think in cross-sections and current density maps, and you have learned to spot a latchup risk or a substrate coupling problem before it ever hits silicon. You are comfortable sitting with a circuit designer who hands you a half-finished schematic and a set of constraints, and you know which questions to ask to turn that into a layout that meets area, performance, and reliability targets. Matching does not scare you, it is something you have done enough times to have opinions about dummy placement and orientation strategies. You have debugged parasitic extraction results at 2 a.m. and lived to tell the story. Automation is not a nice-to-have for you, it is how you stay sane. You write scripts to check spacing rules, generate array structures, or pull reports