R&D Engineering, Staff Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are You have spent years understanding that clock networks are not just routing problems, they are the heartbeat of every chip, and when they fail, everything downstream pays the price. You know the difference between a clock tree that closes timing and one that creates more problems than it solves, and you have debugged enough customer designs to spot the warning signs three steps earlier than most engineers. You are comfortable moving between algorithm development in C++ and customer debug sessions where you need to explain why their skew target is fighting their power budget. You do not just run tools, you understand what the tools are doing under the hood, and when the methodology needs to change, you are the one who figures out what comes next. You like hard problems. Balancing skew, insertion delay, power, and timing across advanced nodes is not a checkbox exercise, it is a series of tradeoffs that require both technical depth and judgment. You ask the right questions, you push back when something does not make sense, and you do not settle for 'good enough' when the design can be better. <p style='--tw-bor