Senior Principal Engineer
- Location
- Noida
- Work mode
- On-site
- Employment type
- Full-time
About the job
Job Description
Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. And will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis.
Should have proficiency in industry-standard DFT tools such as Mentor Tessent , Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. .
Should have experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis . Should be familiar with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG).
Effective communication and teamwork skills, with the ability to collaborate across functions.
#LI-DNI
From US63 NXP USA Inc.'s careers page (Workday), checked 29 Oct 2026.
How to apply
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Posted 12 Oct 2026 · checked 29 Oct 2026 · Report this job