Layout Design, Staff Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of custom layout, working at process nodes where a misplaced contact or a floorplan decision made too quickly shows up months later in silicon. You know that great layout is not just about passing DRC and LVS, it is about understanding how electrons actually move through metal stacks at 7nm and below, and designing for that reality. Leading a layout project does not intimidate you. You have done it before, coordinating across analog designers, verification teams, and foundry partners to deliver PHY IP that meets timing, power, and area targets without compromise. You mentor juniors not by delegating the hard parts but by working alongside them on the critical paths, showing them why matching matters and how to read an EMIR report that actually tells you something. You are comfortable in FinFET and GAA. You understand deep submicron effects well enough to make tradeoff calls in real time. When a floorplan is not working, you do not wait for someone else to fix it. You dig in, you iterate, and you ship. At Synopsys, you will work on next generation DDR, HBM, and UCIe PHY IP that powers the memory and intercon