Senior Staff Digital Methodology Engineer - Design for Testability (DFT)

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are You have spent over a decade architecting test solutions for chips that power everything from autonomous vehicles to data centers, and you understand that DFT is not an afterthought, it is the difference between a design that ships on time and one that bleeds money in yield loss. You know the nuances of scan compression versus hierarchical DFT, not from a textbook, but from making the call on a 10-billion-gate SoC where the wrong decision costs months. You are the person design teams call when ATPG coverage is stuck at 97% and manufacturing is demanding 99.5%. You have debugged IJTAG networks that span multiple chiplets, written the Tcl that automated what used to take three engineers a week, and sat in rooms with VPs explaining why their test access strategy needs to change before tapeout. You do not just know the IEEE standards, you have deployed them in production silicon and lived with the consequences. At Synopsys, you will work on methodologies that define how the world's most complex chips get tested. The problems are hard, the customers are sophisticated, and what you build will matter. <h3 style='--